1. Field of the Invention
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a memory device and a method for testing the memory device.
2. Description of the Related Art
As memory devices become more highly integrated along with the advancements in memory device fabrication technology, the fabricated memory devices may be tested with expensive test equipment for a long time.
Among the test methods is a compressive test, or parallel test, for reducing the time taken for testing a memory device. Hereafter, the compressive test is described.
Testing thousands of cells at a high speed is as important as testing the cells with high reliability. Particularly, not only the time taken for developing a memory device, but also the time taken for testing a memory device directly affects the production cost of the product. Therefore, reducing the testing time is desirable.
Generally, when each cell of a memory chip of a memory device is tested to decide whether or not the memory chip has a failure, the production cost may be high and the time required for testing the memory device may be long.
Herein, a compressive test mode is used to reduce the time taken for testing the memory device. According to the compressive test method, the same data are written in a plurality of cells and then when the data are read, an exclusive OR logic gate (i.e., an XOR logic gate) is used. When the same data are read from the multiple cells, a ‘1’ may be returned thereby determining that the memory device has passed the compressive test. Otherwise, if a different data is read from any one of the cells, a ‘0’ may be returned thereby determining that the memory device has failed the compressive test.
Such a parallel test requires activating many banks all at once and performing a data read/write operations. According to conventional test technology, the data outputted from several banks pass through the above-described compressive process and are outputted through the respective interface pads corresponding to the banks. The test equipment then makes a pass/failure decision for the memory device in response to the data outputted from the interface pads.
For example, when it is assumed that one chip includes 8 banks and a compressive test is performed by outputting data from the 8 banks, the data are outputted through 8 interface pads. If test equipment includes 64 interface pads, the test equipment cannot help but test 8 chips at once.
In short, generally the number of interface pads of the test equipment equals the number of banks included in one chip, or the number of banks activated for one-time testing in one chip. And since it is not possible to test many chips all at once, it may take a long time to perform the conventional compressive test.